The present invention relates to control of buses in a data processing system and more particularly to an address bus control apparatus facilitating accessing between units using address data of different widths or lengths.
A data processing system with multi-buses, organized with a microprocessor in the center, frequently includes a bus (memory bus) connecting the microprocessor and a memory, a bus (system bus) interconnecting input/output units, and driver gates or buffer gates disposed between these buses. For example, a system as disclosed in Japanese Laid-open Patent Publication No. 60-235268 includes an internal bus connected with the CPU and an external bus connected with external input/output units, and address bus buffers and data bus buffers connecting these buses. Both these buses have the same address bus width, that is, the same number of address bits transmitted over the address bus. The most significant bit of the address data issued by the CPU onto the internal bus indicates which bus is to be accessed. There is provided a bank setting address switch or register, which delivers one address bit substituting for the most significant address bit used as the bus selecting information to be placed onto the address bus of the external bus, whereby the address space accessible through the buses is expanded.
With an increase in the word length of the microprocessor and improvement in its performance, the width (number of bits) of the address data, that is, the size of the address space handled thereby is expanded. Recently, a microprocessor capable of handling a 32-bit address, an address space of 4 GB, has become available. Such an expanded address space is too large for ordinary input/output units. Hence, it is desired that the address bus width of the system bus with which input/output units are connected is made smaller than the address bus width of the memory bus with which the CPU and the memory are connected, for example, 28 bits (256 MB).
Among input/output units that are desired to be connected to a system bus, there are those developed for use with old-type microprocessors having different sizes of address space, and therefore, there may be included such input/output units as will use address data of a still smaller width than the aforementioned reduced address bus width of the system bus.
In a system wherein such units using different address data widths are connected with two buses having address buses of different widths, there arises a problem of mismatching of the address data widths. Generally, when there is a mismatch between address data widths, it becomes impossible to carry out correct addressing. Where the address bus width of a bus is larger than the address data width of a unit connected to that bus, it may be possible to provide a register for supplying the address bits to make up for the difference therebetween, thereby compensating for a mismatch between address data widths of units connected to a single bus and using different address data widths. However, in a system wherein such units are connected to two buses of different address data widths, i.e., the memory bus and the system bus, there arises an additional problem of a mismatch between the address bus widths of these buses. Thus, it becomes difficult to achieve efficient control of DMA (direct memory access) from any unit connected with any bus to any other unit connected with any bus. What is demanded in particular is to make it possible that a unit which is connected to the system bus having the smaller address bus width and which uses address data of a still smaller width than the address bus width of the system bus can dynamically and quickly select any of the units connected to either of the system bus and the memory bus, as the object unit of DMA.
Accordingly, an object of the present invention is to provide an address bus control apparatus capable of efficiently controlling accesses between units using different address data widths and connected with buses of different address bus widths.
Another object of the present invention is to provide an address bus control apparatus whereby a unit connected with one of the two buses having the smaller address bus width and using address data of a still smaller width than the address bus width of this bus can dynamically and quickly select any of the units connected to either the same bus or the other bus having the larger address bus width.